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Alif Semiconductor /AE302F40C1537LE_CM55_HE_View /ADC120 /ADC_CLK_DIVISOR

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Interpret as ADC_CLK_DIVISOR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLK_DIVISOR

Description

ADC Clock Divider Value Register

Fields

CLK_DIVISOR

Clock divider applied to input clock: Others: Reserved

2 (Val_0x2): Divide by 2

3 (Val_0x3): Divide by 3

16 (Val_0x10): Divide by 16

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THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data